Test Generation for Sequential Circuits under IDDQ Testing(Special Issue on Test and Diagnosis of VLSI)

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概要

• 論文の詳細を見る

• This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.

• 社団法人電子情報通信学会の論文
• 1998-07-25

著者

• Kinoshita Kozo

  The Faculty Of Engineering Osaka University

• MAEDA Toshiyuki

  the Faculty of Engineering, Osaka University

• HIGAMI Yoshinobu

  the Faculty of Engineering, Osaka University

• Higami Yoshinobu

  The Faculty Of Engineering Osaka University

• Maeda Toshiyuki

  The Faculty Of Engineering Osaka University

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• Test Generation for Sequential Circuits under IDDQ Testing(Special Issue on Test and Diagnosis of VLSI)
• Test Sequence Generation for Sequential Circuits with Distinguishing Sequences (Special Section on VLSI Design and CAD Algorithms)

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