Ethernet Over HDLC Forwarding VLSI for Network Access System
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概要
- 論文の詳細を見る
In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 μm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.
- 2002-07-01
著者
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Park S‐h
Yonsei Univ. Seoul Kor
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Kang Wooseok
It Soc Center
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Park Sang-hui
Department Of Electrical And Computer Engineering Yonsei University
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Oh Jinsung
School Of Electrical Eng. Halla Univ.
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HONG Minsuk
Department of Electrical and Electronic Eng., Yonsei Univ.
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PARK Chan
Information and Communication Division, Hallym Univ.
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RHEE Sehyeon
IT SOC Center
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Hong Minsuk
Department Of Electrical And Electronic Eng. Yonsei Univ.
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Park Chan
Information And Communication Division Hallym Univ.
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