Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier (Special Section on Analog Circuit Techniques and Related Topics)
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概要
- 論文の詳細を見る
This paper presents a new scheme of a low power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than l2mW at 20MSample/s.
- 社団法人電子情報通信学会の論文
- 1999-02-25
著者
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Miyazaki Daisuke
Department Of Applied Physics Faculty Of Engineering Osaka University
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Miyazaki Daisuke
Department Of Information And Computer Sciences Toyohashi University Of Technology
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Tadokoro Yoshiaki
Department Of Information And Computer Sciences/intelligent Sensing System Research Center Toyohashi
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Tadokoro Yoshiaki
Department Of Information And Computer Sciences Toyohashi University Of Technology
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KAWAHITO Shoji
Department of Information and Computer Sciences, Toyohashi University of Technology
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Kawahito Shoji
Department Of Electrical And Electronic Engineering Toyohashi University Of Technology
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