Low-Power Architectures for Programmable Multimedia Processors (Special Section on VLSI for Digital Signal Processing)

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概要

• 論文の詳細を見る

• This paper describes low-power architecture methodologies for programmable multimedia processors, which will become major functional units in System-On-a-Chip. After brief review on multimedia processing and low-power consider ations, recent programmable chips, including MPUs and DSPs, are investigated in terms of low-power implementation. In order to show the difference of the low-power approaches between programmable processors and ASIC processors, a single-chip MPEG 2 encoder is also included as an example of ASIC design.

• 社団法人電子情報通信学会の論文
• 1999-02-25

著者

• Nishitani Takao

  Nec Silicon Systems Research Labs.

関連論文

• Low-Power Architectures for Programmable Multimedia Processors (Special Section on VLSI for Digital Signal Processing)

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