Dual-Loop Digital PLL Design for Adaptive Clock Recovery (Special Section on VLSI Design and CAD Algorithms)

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概要

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• Since most digital phase-locked loops (DPLLs) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady-state, the DPLL loop bandwidth is preferred to being adjusted accordingly. In this paper, a bandwidth adjusting (adaptive) algorithm is presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardweare requirement. This algorithm, based on the recursive least squares (RLS) criterion, suggest an optimal sequence of control parameters for a dualloop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant. The algorithm can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drivers that require a short initial preamble period.

• 1998-12-25

著者

• Kim Tae

  The Electrical Engineering Department At Kaist

• KIM Beomsup

  the Electrical Engineering Department at KAIST

関連論文

• Dual-Loop Digital PLL Design for Adaptive Clock Recovery (Special Section on VLSI Design and CAD Algorithms)
• Optimal Loop Bandwidth Design for Low Noise PLL Applications (Special Section on VLSI Design and CAD Algorithms)

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