"FASTOOL" an FIR Filter Compiler Based on the Automatic Design of the Multi-Input-Adder

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概要

• 論文の詳細を見る

• We have developed a method to automatically generate a multi-input-adder circuit for an irregular array of partial products. "FASTOOL," an FIR Filter Automatic Synthesis TOOL for an HDL design environment, is proposed for use with this method and with conventional filter coefficient design programs. Filter design from specifications to the structure of Verilog-HDL has been automated. It is possible for a system designer to quickly perform filter LSI optimization by balancing cost and performance.

• 社団法人電子情報通信学会の論文
• 1995-12-25

著者

• Kondo Yoshihito

  Pvp Project Research Center Sony Corporation

• Yamazaki Takao

  PVP Project, Research Center, Sony Corporation

• Igota Sayuri

  PVP Project, Research Center, Sony Corporation

• Iwase Seiichiro

  PVP Project, Research Center, Sony Corporation

• Iwase S

  Sony Corp. Tokyo Jpn

• Yamazaki Takao

  Pvp Project Research Center Sony Corporation

• Igota Sayuri

  Pvp Project Research Center Sony Corporation

関連論文

• "FASTOOL" an FIR Filter Compiler Based on the Automatic Design of the Multi-Input-Adder

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