An Architecture for High Speed Array Multiplier

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概要

• 論文の詳細を見る

• High speed multiplication of two n-bit numbers plays an important role in many digital signal processing applications. Traditional array and Wallace multipliers are the most widely used multipliers implemented in VLSI. The area and time (=latency) of these two multipliers depend on operand bit-size, n. For a particular bit-size, they occupy fixed positions in some graph which has area and time along the x and y-axes respectively. However, many applications require a multiplier which has an 'intermediate' area-time characteristics with the above two traditional multipliers occupying two extreme ends of above mentioned area-time curve. In this paper, we propose such an intermediate multiplier which trades off area for time. It has higher speed (i.e., less latency) but more area than a traditional array multiplier. Whereas when compared with a traditional Wallace multiplier, it has lower speed and area. The attractive point of our multiplier is that, it resembles an array multiplier in terms of regularity in placement and inter-connection of unit computation cells. And its interesting feature is that, in contrast to a traditional array multiplier, it computes by introducing multiple computation wave fronts among its computation cells. In this paper, we investigate on the area-time complexity of our proposed multiplier and discuss on its characteristics while comparing with some contemporary multipliers in terms of latency, area and wiring complexity.

• 社団法人電子情報通信学会の論文
• 1993-08-25

著者

• Tamaru Keikichi

  The Faculty Of Engineering Kyoto University

• Islam Farhad

  NTT Human Interface Laboratories

関連論文

• An Architecture for High Speed Array Multiplier
• Design of a Multiplier-Accumulator for High Speed Image Filtering

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