A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning

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概要

• 論文の詳細を見る

• This paper describes a novel but simple method of implementing waveform relaxation technique for bipolar circuits involving ECL gates. This method performs gate level partitioning of ECL circuits not only during the cutoff state of the input transistor but also when the input transistor is in its active state. Partitioning at all times has become possible due to the favorable property of input and output stages of ECL gates. It is shown that this method is faster than direct method even when the circuits containing only few gates is simulated. Further, it is shown that the present method is applicable to the case where the interconnections between the ECL gates is treated as lossy transmission lines.

• 一般社団法人電子情報通信学会の論文
• 1993-04-25

著者

• Asai Hideki

  The Faculty Of Engineering Shizuoka University

• Bandi VijayaGopal

  the Faculty of Engineering, Shizuoka University

• Bandi V

  Shizuoka Univ. Hamamatsu‐shi Jpn

• Bandi Vijayagopal

  The Faculty Of Engineering Shizuoka University

関連論文

• Mixed Mode Circuit Simulation Using Dynamic Partitioning (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
• Relaxation-Based Circuit Simulation Techniques in the Frequency Domain
• A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning
• Acceleration Techniques for Waveform Relaxation Analysis of RLCG Transmission Lines Driven by Bipolar Logic Gates

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