Simulation of Power-Law Relaxations by Analog Circuits : Fractal Distribution of Relaxation Times and Non-integer Exponents

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概要

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• Power-law decay of current for the application of step-function voltage observed for amorphous materials can be expressed by an admittance s^a(0<a<1) of a linear diode using complex angular frequency s. It is shown that power-law decay can be interpreted as a superposition of exponential decays having fractally distributed relaxation times and simulated using RC networks. By use of a similar manner, admittance s^<-b> (0< b<1) showing the relation of duality can be simulated using RL networks. According to these methods, we can synthesize the admittance involving non-integer exponents systematically.

• 社団法人電子情報通信学会の論文
• 1993-02-25

著者

• Sugi Michio

  The Electrotechnical Laboratory

• Saito K

  Electrotechnical Laboratory

• Saito Kazuhiro

  the Electrotechnical Laboratory

関連論文

• Simulation of Power-Law Relaxations by Analog Circuits : Fractal Distribution of Relaxation Times and Non-integer Exponents
• √-Variation of AC Admittance inthe Inhomogeneously Distributed RC Lines
• Simulation of Fractal Immittance by Analog Circuits: An Approach to the Optimized Circuits

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