Design of a Multiplier-Accumulator for High Speed Image Filtering

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概要

• 論文の詳細を見る

• Multiplication-accumulation is the basic computation required for image filtering operations. For real-time image filtering, very high throughput computation is essential. This work proposes a hardware algorithm for an application-specific VLSI architecture which realizes an area-efficient high throughput multiplier-accumulator. The proposed algorithm utilizes a priori knowledge of filter mask coefficients and optimizes number of basic hardware components (e.g., full adders, pipeline latches, etc.). This results in the minimum area VLSI architecture under certain input/output constraints.

• 社団法人電子情報通信学会の論文
• 1993-11-25

著者

• Tamaru Keikichi

  The Faculty Of Engineering Kyoto University

• Islam FarhadFuad

  NTT Human Interface Laboratories

• Islam F

  Ntt Human Interface Laboratories

関連論文

• An Architecture for High Speed Array Multiplier
• Design of a Multiplier-Accumulator for High Speed Image Filtering

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