Hierarchical Analysis System for VLSI Power Supply Network (Special Section on VLSI Design and CAD Algorithms)

概要

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Since, in a VLSI circuit, the number of transistors and the clock frequency are constantly increasing, it is important to analyze the voltage drop and current density on a full chip's power networks. We propose a new hierarchical power analysis system named XPOWER. A new reduction algorithm for the resistance and current source network is used in this system. The algorithm utilizes the design hierarchy in nature and is independent of network topology. Networks at each level are reduced into small and equivalent networks, and this reduction is performed recursively from the bottom levels of the design hierarchy. At each step of the reduction, the network under consideration consists of two kinds of objects: (1) reduced child networks, and (2) the interconnection between child networks. After all networks have been reduced, circuit equations are solved recursively from the top. This allows to decrease the size of the matrix to be solved and to reduce the execution time. Experimental results show that the factor of reduction in matrix size is from 1 / 10 to 1 / 40 and execution is six times faster than with flat analysis. The power networks of a 16 bit digital signal processor was analyzed within 15 minutes using XPOWER.
社団法人電子情報通信学会の論文
1993-10-25