Threshold Voltage Mismatch of FD-SOI MOSFETs(<Special Section>Analog Circuit and Device Technologies)

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概要

• 論文の詳細を見る

• The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.

• 社団法人電子情報通信学会の論文
• 2004-06-01

著者

• TANIGUCHI Kenji

  the Graduate School of Engineering, Osaka University

• Taniguchi Kenji

  The Graduate School Of Engineering Osaka University

• SHIMIZU Yoshiyuki

  the Graduate School of Engineering, Osaka University

• MATSUOKA Tashimasa

  the Graduate School of Engineering, Osaka University

• Matsuoka Tashimasa

  The Graduate School Of Engineering Osaka University

• Shimizu Yoshiyuki

  The Graduate School Of Engineering Osaka University

関連論文

• A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula(Microelectronic Test Structures)
• Threshold Voltage Mismatch of FD-SOI MOSFETs(Analog Circuit and Device Technologies)

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