A Precision CMOS Power-On-Reset Circuit with Power Noise Immunity for Low-Voltage Technology(Electronic Circuits)

概要

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In this era of System-On-a-Chip (S OC) technology, a designable initial state is required. Thus, embedding low voltage and low power Power-On-Reset (FOR) circuit on the SOC chip is important for the portable device. This paper proposes a new FOR circuit with process and temperature compensations. A band-gap reference is used in this circuit to reduce the effect of the temperature and process variations. With 200 mV hysteretic design provides robust noise immunity against voltage fluctuations on the power supply. The POR circuit has been designed, simulated, and implemented. A test chip has been fabricated by using 0.18μm single-poly triple-metal CMOS logical process. Measurement results show the rise threshold voltage V_<rr> has only a 3% variation under the temperature range from -40℃ to 125℃. The power consumption is 39mW atthe 1.8V power supply. The chip size of the FOR is 62mm × 280mm. Thus, this FOR circuit has a great potential to apply to a low power supply system.
社団法人電子情報通信学会の論文
2004-05-01