Circuit Partition and Reordering Technique for Low Power IP Design(<Special Section>Low-Power System LSI, IP and Related Technologies)

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概要

• 論文の詳細を見る

• Circuit partition, retiming and state reordering techniques are effective in reducing power consumption of circuits. In this paper, we propose a partition architecture and a methodology to reduce power consumption when designing low power IP, named PRC (Partition and Reordering Circuit). The circuit reordering synthesis flow consists of three phases: first, evenly partition the circuit based on the Shannon expansion; secondly encode the output vectors of each partition to build an equivalent functional logic. Finally, apply reordering algorithm to reorganize the logic function to reduce power consumption and decrease area cost. The validity of our architecture is proven by applying it to MCNC benchmark with simulation environment.

• 社団法人電子情報通信学会の論文
• 2004-04-01

著者

• Huang Chun-ming

  Department Of Computer Science And Information Engineering National Taiwan University

• Lai Feipei

  Department Of Computer Science And Information Engineering National Taiwan University

• Ruan Shanq-jang

  Department Of Electronic Engineering National Taiwan University Of Science And Technology

• TSAI Kim-Lin

  Department of Electrical Engineering, National Taiwan University

• NAROSKA Edwin

  Department of Electrical Engineering, Computer Engineering Institute, University of Dortmund

• Tsai Kim-lin

  Department Of Electrical Engineering National Taiwan University

• Naroska Edwin

  Department Of Electrical Engineering Computer Engineering Institute University Of Dortmund

• Lai Feipei

  Department Of Electrical Engineering National Taiwan University:department Of Computer Science And I

• RUAN Shanq-Jang

  Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology

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