An 8b 200 MHz Time-Interleaved Subranging ADC Based on a Single-Poly Digital CMOS Process

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概要

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• This work describes an 8b 200 MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase the sampling speed and a new reference voltage switching scheme to reduce the settling time of the reference voltages and the chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves the linearity and the settling time of the reference voltages simultaneously. The proposed sample-and-hold amplifier employs an input dynamic common mode feedback circuit for high dynamic performance, based on conventional common-drain amplifiers and passive differential circuits.

• 社団法人電子情報通信学会の論文
• 2003-03-01

著者

• Lee Seung-hoon

  Sogang University

• Moon Jung-woong

  Sogang University:(present Address)tli Inc.

関連論文

• An 8b 200 MHz Time-Interleaved Subranging ADC Based on a Single-Poly Digital CMOS Process

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