A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free
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概要
- 論文の詳細を見る
A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-μm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.
- 社団法人電子情報通信学会の論文
- 2003-03-01
著者
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Yang Sung-hyun
Department Of Computer And Communication Engineering Chungbuk National University
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CHO Kyoung-Rok
Department of Computer and Communication Engineering, Chungbuk National University
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YOU Younggap
Department of Computer and Communication Engineering, Chungbuk National University
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Cho K‐r
Chungbuk National Univ. Kor
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Cho K‐r
Chungbuk Nat'l Univ. Chungbuk‐do Kor
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Cho Kyoung-rok
Department Of Computer And Communication Engineering Chungbuk National University
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You Younggap
Department Of Computer And Communication Engineering Chungbuk National University
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YANG Sung-Hyun
Department of Computer and Communication Engineering,Chungbuk National University
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