Address Computation in Configurable Parallel Memory Architecture(Networking and System Architectures)(<Special Section>Hardware/Software Support for High Performance Scientific and Engineering Computing)

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概要

• 論文の詳細を見る

• Parallel memories increase memory bandwidth with several memory modules working in parallel and can be used to feed a processor with only necessary data. The Configurable Parallel Memory Architecture (CPMA) enables a multitude of access formats and module assignment functions to be used within a single hardware implementation, which has not been possible in prior embedded parallel memory systems. This paper focuses on address computation in CPMA, which is implemented using several configurable computation units in parallel. One unit is dedicated for each type of access formats and module assignment functions that the implementation supports. Timing and area estimates are given for a 0.25-micron CMOS process. The utilized resources are shown to be linearly proportional to the number of memory modules.

• 一般社団法人電子情報通信学会の論文
• 2004-07-01

著者

• Hamalainen Timo

  Institute Of Digital And Computer Systems Tampere University Of Technology

• AHO Eero

  Institute of Digital and Computer Systems, Tampere University of Technology

• VANNE Jarno

  Institute of Digital and Computer Systems, Tampere University of Technology

• KUUSILINNA Kimmo

  Institute of Digital and Computer Systems, Tampere University of Technology

• Aho Eero

  Institute Of Digital And Computer Systems Tampere University Of Technology

• Vanne Jarno

  Institute Of Digital And Computer Systems Tampere University Of Technology

• Kuusilinna Kimmo

  Institute Of Digital And Computer Systems Tampere University Of Technology

関連論文

• Address Computation in Configurable Parallel Memory Architecture(Networking and System Architectures)(Hardware/Software Support for High Performance Scientific and Engineering Computing)

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