Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure(Computer System Element)

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概要

• 論文の詳細を見る

• This paper presents a new asynchronous multiplier. The original array structure is divided into two asymmetric arrays, called an upper array and a lower array. For the lower array, Left to Right scheme is applied to take advantage of a fast computation and low power consumption as well. Simulation results show that the proposed multiplier has 40% of performance improvement with a relatively lower power consumption. The multiplier has been implemented in a CMOS 0.35μm technology and proved functionally correct.

• 社団法人電子情報通信学会の論文
• 2003-07-01

著者

• Lee Dong-ik

  Department Of Information And Communications Gwangju Institute Of Science And Technology

• Lee Dong-ik

  Department Of Information And Communications Kwang-ju Institute Of Science And Technology

• KIM Suk-Jin

  Department of Information and Communications, Gwangju Institute of Science and Technology

• Kim Suk-jin

  Department Of Information And Communications Kwang-ju Institute Of Science And Technology

• Park Chan-Ho

  Electronics arid Telecommunications Research Institute

• Choi Byung-Soo

  Department of Information and Communications, Kwang-Ju Institute of Science and Technology

• Jung Eun-Gu

  Department of Information and Communications, Kwang-Ju Institute of Science and Technology

• Jung Eun-gu

  Department Of Information And Communications Kwang-ju Institute Of Science And Technology

• Choi Byung-soo

  Department Of Information And Communications Kwang-ju Institute Of Science And Technology

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