B-Ternary Asynchronous Digital System under Relativity Delay

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Some of the recent digital systems have a serious clock skew problem due to huge hardware implementation and high-speed operation in VLSI's. To overcome this problem, clock distribution techniques and, more notably, asynchronous system design methodologies have been investigated. Since the latest asynchronous digital systems use two-rail logic with two-phase data transfer manner, more than two-fold hardware is required in comparison with the synchronous system. In this article, we present adesign of asynchronous digital system which is based on B-ternary logic that can process binary data. The system which is based on speed-independent mode consists of data-path and its controller. Then we provide B-ternary two-phase binary data processing in the data-path and its control procedure with hand-shake protocol. To implement the system some functional elements are presented, that is a ternary-in/binary-out register with request/acknowledge circuits and a control unit. These functional elements are fabricated with ternary NOR, NAND, INV gates and ternary-in/binary-out D-FF (D-elements). The B-ternary based asynchronous circuit has less interconnections, achives race-free operations and makes use of conventional binary powerful design tools. Particularly, we extend the speed-independent delay model to relativity delays in order to reduce hardware overhead of checking memory stability in the system. As a concrete example, a carry-complection type asynchronous adder system is demonstrated under extended speed-independent mode to show the validity of the extension.
社団法人電子情報通信学会の論文
2003-05-01

B-Ternary Asynchronous Digital System under Relativity Delay

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