Timing-Driven Placement Based on Path Topology Analysis(VLSI Design Technology and CAD)
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概要
- 論文の詳細を見る
A timing-driven placement algorithm based on path topology analysis is presented. The optimization for path delay is transformed into cell location optimization. The algorithm pays much attention on path topologies and applies an effective force directed method to find cell target locations. Total wire length optimization is combined with the timing-driven placement algorithm. MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks are experimented and results show that our timing-driven placement algorithm can make the longest path delay improve up to 13% compared with wirelength driven placement.
- 社団法人電子情報通信学会の論文
- 2005-08-01
著者
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Mao Junfa
Department Of Electronic Engineering Shanghai Jiao Tong University
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Mao Junfa
Department Of Electronic Engineering Shanghai Jiaotong University
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CHENG Feng
Department of Electronic Engineering, Shanghai Jiaotong University
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LI Xiaochun
Department of Electronic Engineering, Shanghai Jiaotong University
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Cheng Feng
Department Of Electronic Engineering Shanghai Jiaotong University
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Li Xiaochun
Department Of Electronic Engineering Shanghai Jiaotong University
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LI Xiaochun
Department of Economics, Nanjing University. The authors express thanks to the anonymous referee for the constructive suggestions and comments. This article is sponsored by the National Social Sciences Fund Project No. 10BJL035 and Key Project of 2009 f
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