Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism(VLSI Design Technology and CAD)
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概要
- 論文の詳細を見る
Conventional delay-insensitive (DI) data encodings require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, a DI data transfer mechanism based on current-mode multiple valued logic (CMMVL), where N-bit data transfer can be performed with only N+1 wires, is proposed. The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25-μm CMOS technology. Simulation results with wire lengths of 4mm or larger demonstrate that the CMMVL scheme significantly reduces delay-power product values of the dual-rail encoding with data rate of 5MHz or more and the 1-of-4 encoding with data rate of 18MHz or more.
- 社団法人電子情報通信学会の論文
- 2005-05-01
著者
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HAR Dong
Department of Information and Communications, Gwangju Institute of Science and Technology
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Har Dong
Department Of Information And Communications Gwangju Institute Of Science And Technology
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Har Dong
Department Of Information And Communications Gwangju Institute Of Science And Technology (gist)
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Oh Myeong
Department Of Information And Communications Gwangju Institute Of Science And Technology (gist)
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