Design of Decoupled Wrapper for Globally Asynchronous Locally Synchronous Systems(<Special Section>Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC 2003))

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概要

• 論文の詳細を見る

• In this paper, we propose an advanced structure of the interface circuit, called a wrapper, for Globally Asynchronous Locally Synchronous (GALS) systems. The proposed wrapper is composed of a sender module and a receiver module. The sender module carries out data transfers in an efficient way by decoupling dependency between an external handshake protocol and an internal clock. The decoupling effect allows the external handshake protocol and the internal clock to be executed in a concurrent way and hence allows the wrapper to show better performance. We have designed our wrapper at the transistor level with 0.35-μm technology. When we compare our decoupled wrapper with two conventional wrappers based on pausible clocking scheme, our simulation results show that performance improvement is about 8-13% and 13-56%, respectively.

• 社団法人電子情報通信学会の論文
• 2004-06-01

著者

• Lee Dong-ik

  Department Of Information And Communications Gwangju Institute Of Science And Technology

• Lee Dong-ik

  Department Of Information And Communications Kwangju Institute Of Science And Technology (kjist)

• CHOI Ho-Yong

  School of Electrical & Computer Eng., Chungbuk National University

• Choi Ho-yong

  School Of Electrical & Computer Eng. Chungbuk National Univ.

• Park S‐j

  Ajou Univ. Suwon Kor

• Oh Myeong-hoon

  Department Of Information And Communications Kwangju Institute Of Science And Technology (kjist)

• PARK Seok-Jae

  School of Electrical & Computer Eng., Chungbuk National Univ.

関連論文

• An Efficient State Space Search for the Synthesis of Asynchronous Circuits by Subspace Construction
• Test Generation for SI Asynchronous Circuits with Undetectable Faults from Signal Transition Graph Specification(Special Section on Papers Selected from ITC-CSCC 2000)
• Synthesis for Testability of Synchronous Sequential Circuits with Strong-Connectivity Using Undefined States on State Transition Graph(Test)(VLSI Design and CAD Algorithms)
• High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph(Special Section on VLSI Design and CAD Algorithms)
• Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure(Computer System Element)
• Design of Decoupled Wrapper for Globally Asynchronous Locally Synchronous Systems(Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC 2003))
• One-Time Key Generation System for Agent Data Protection

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