All Digital DLL with Three Phase Tuning Stages(<Special Section>Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC 2003))

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概要

• 論文の詳細を見る

• This paper describes an all-digital DLL (Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35 μm CMOS technology under 3.3 V power supply. The simulation result shows the maximum phase error can be reduced to 13-42ps with the operating range of 250MHz to 800MHz.

• 社団法人電子情報通信学会の論文
• 2004-06-01

著者

• Kang Jin-Ku

  School of Electronics Engineering, Inha University

• Choi Jin-ho

  School Of Electrical And Computer Engineering Inha University

• Kang Jin-ku

  School Of Electrical And Computer Engineering Inha University

関連論文

• SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators
• A Delay Locked Loop Circuit with Mixed Mode Phase Tuning Technique
• All Digital DLL with Three Phase Tuning Stages(Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC 2003))
• A 4Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement

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