A Modeling Methodology and Body Effect Analysis for Hot-Carrier Reliability Simulation of Logic Circuits

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概要

• 論文の詳細を見る

• A drain avalanche hot carrier lifetime model including a body effect caused by secondary hot electrons has been developed. It has been confirmed that the proposed model fits a wide range of experimental data using a small number of parameters. The model provides a practical modeling methodology for reliability simulation based on parameter extraction at maximum substrate current conditions alone. Simulation accuracy produced by the methodology has been experimentally verified using ring oscillators including NAND gates. It has been demonstrated that simulation accuracy of degradations has become by 0.34 decade better using the new methodology than using that based on the conventional_τI_d/W-I_<sub>/I_d model.

• 社団法人電子情報通信学会の論文
• 2002-06-01

著者

• Koike Norio

  Ulsi Process Technology Development Center Semiconductor Company Matsushita Electric Industrial Co.

• YONEZAWA Hirokazu

  ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electric Industrial Co

• Yonezawa Hirokazu

  Ulsi Process Technology Development Center Semiconductor Company Matsushita Electric Industrial Co.

関連論文

• A Test Structure for Two-Dimensional Analysis of MOSFETs by Hot-Carrier-Induced Photoemission(Microelectronic Test Structures)
• A New Test Structure for Precise Location Measurement of Hot-Carrier-Induced Photoemission Peak in Subquarter-Micron MOSFETs(Special Issue on Microelectronic Test Structures)
• A Simulation Methodology for Bidirectional Hot-Carrier Degradation in a Static RAM Circuit
• A Modeling Methodology and Body Effect Analysis for Hot-Carrier Reliability Simulation of Logic Circuits

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