Fabrication of 100 nm Width Fine Active-Region Using LOCOS Isolation(Special Issue on Advanced Sub-0.1μm CMOS Devices)

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概要

• 論文の詳細を見る

• We have investigated fabricating fine active regions by tuning process condition of conventional LOCOS for the fabrication of the gate width 100nm MOSFET. Considering the lowering in fluidity of silicon dioxide, oxidation temperature was changed to 900℃ which is lower than conventional 1000℃. In addition active region shape was modified to utilize vertical stress due to nitride elastic force. As a result, 75nm width fine active region was successfully fabricated. Though lowering of the oxidation temperature tends to increase stress, junction leakage current and gate oxide reliability showed no degradation. On the other hand, PSL (Poly-Si Sidewall LOCOS) gave rise to degradation in the electrical properties by the stress. Using the LOCOS process, we have fabricated the MOSFETs with the fine active regions.

• 社団法人電子情報通信学会の論文
• 2002-05-01

著者

• SHIBAHARA Kentaro

  the Research Center for Nanodevices and Systems, Hiroshima University

• Shibahara K

  Research Center For Nanodevices And Systems Hiroshima University

• Aoki Y

  The Reserch Center For Nanodevices And Systems Hiroshima University

• NOTSU Daisuke

  The Reserch Center for Nanodevices and Systems, Hiroshima University

• IKECHI Naoya

  The Reserch Center for Nanodevices and Systems, Hiroshima University

• AOKI Yasuyuki

  The Reserch Center for Nanodevices and Systems, Hiroshima University

• KAWAKAMI Nobuyuki

  The Electronics Research Laboratory, Kobe Steel Corporation

• Ikechi Naoya

  The Reserch Center For Nanodevices And Systems Hiroshima University

• Notsu Daisuke

  The Reserch Center For Nanodevices And Systems Hiroshima University

• Kawakami Nobuyuki

  The Electronics Research Laboratory Kobe Steel Corporation

• Shibahara K

  Hiroshima Univ. Higashihiroshima‐shi Jpn

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