A 100 nm Node CMOS Technology for System-on-a-Chip Applications(Special Issue on Advanced Sub-0.1 μm CMOS Devices)

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概要

• 論文の詳細を見る

• We have developed 100nm node CMOS technology, consisting of a 65nm gate length and a 1.6 nm gate oxide thickness. The major transistor design issue is how to maintain drive current at supply voltage of only 1.0V, while suppressing standby leakage current to a practical level for system-on-a-chip applications. In order to obtain thinner electrical equivalent oxide thickness with well-suppressed gate leakage current, we have adopted radical nitridation and poly-SiGe. We have also utilized low-energy ion-implantation, low-temperature CVD, and spike RTA technology to overcome the short channel effect. With supply voltage of 1.0V, our generic transistor shows the drive current of 520/196μA/μm with the off current of 0.5nA/μm. We also designed high-speed (I_<off> = 5 nA/μm), ultrahigh-speed (I_<off> = 30nA/μm) transistors, and low-standby power (I_<off> = 5pA/μm), all of which can be deployed on the same chip.

• 社団法人電子情報通信学会の論文
• 2002-05-01

著者

• Imai K

  Ulsi Device Development Division Nec Corporation

• Imai Kiyotaka

  Ulsi Device Development Laboratories Nec Corporation

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• A 100 nm Node CMOS Technology for System-on-a-Chip Applications(Special Issue on Advanced Sub-0.1 μm CMOS Devices)
• Phosphorus-Assisted Low-Energy Arsenic Implantation Technology for N-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Source/Drain Formation Process

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