Low Power CMOS Design Challenges

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概要

• 論文の詳細を見る

• Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

• 社団法人電子情報通信学会の論文
• 2001-08-01

著者

• Kuroda Tadahiro

  The Author Is With The Department Of Electrical Engineering Keio University

関連論文

• Low Power CMOS Design Challenges

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