RAM BIST

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概要

• 論文の詳細を見る

• This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: 1. Can be used in both built-in mode and off chip/module mode. 2. Can be used to test and diagnose naked arrays. 3. Fault diagnosis is simple and is "free" for some faults during test. 4. Is never subject to aliasing. 5. Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. 6. If used as built-in feature, it does not slow down the normal operation of the array. 7. Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. 8. If used as a built-in feature, the hardware overhead is very low.

• 社団法人電子情報通信学会の論文
• 2001-01-01

著者

• Savir J

  New Jersey Inst. Technol. Nj Usa

• SAVIR Jacob

  The author is with ECE Department, New Jersey Institute of Technology, University Heights, Newark

関連論文

• RAM BIST

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