Systematic Yield Simulation Methodology Applied to Fully-Depleted SOI MOSFET Process (Special lssue on SISPAD'99)
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, we propose an effective SOI yield engineering methodology by practical usage of 2D simulations. Process design for systematic yield of Fully-Depleted SOI MOSFET requires specific consideration of floating-body effects and parasitic channel leakage currents. The influence of varied SOI layer thickness to such phenomena is also complicated and substantial. Instead of time-consuming 3D simulators, 2D simulators are used to optimize the process considering these effects in acceptable turn around time. Our methodology is more effective in future scaled-down process with decreased SOI layer thickness.
- 社団法人電子情報通信学会の論文
- 2000-08-25
著者
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MIURA Noboru
Department of Electronics and Bioinformatics, Science and Technology, Meiji University
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Miura N
Department Of Materials Science And Technology Graduate School Of Engineering Sciences Kyushu Univer
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Fukuda K
Oki Electric Industry Co. Ltd.
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Miura Noriyuki
Oki Electric Industry Co. Ltd.
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Miura N
Department Of Electronics And Bioinformatics Science And Technology Meiji University
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Miura Naruhisa
Advanced Technology R&d Center Mitsubishi Electric Corporation
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HAYASHI Hirokazu
OKI Electric Industry Co., Ltd.
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FUKUDA Koichi
OKI Electric Industry Co., Ltd.
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Nishi Kenji
OKI Electric Industry Co., Ltd.
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Nishi K
Sumitomo Electric Hightechs Co. Ltd. Itami‐shi Jpn
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Hayashi H
Oki Electric Industry Co. Ltd.
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Nishi Kenji
Oki Electric Industry Co. Ltd.
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Hayashi Hitoshi
Ntt Corp. Yokosuka‐shi Jpn
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