Improvement of E-Beam Observability by Testing-Pad Placement in LSI Design Layout

概要

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A novel testing-pad placement method has been developed to greatly improve E-beam observability for multi-level wiring LSIs. In the method, testing pads connecting a lower-metal-layer wire with a top-metal-layer electrode are positioned in the design layout, making removal of the insulator unnecessary. The method features i) pad placement in unoccupied areas in mask patterns to avoid increases in chip size, ii) minimized pad size through the use of stacked vias so that the pads can be placed on as many wire nodes as possible, iii) placement as far as possible from the nearby wircs to avoid local field effects, and iv) allocation of one testing pad to one circuit node to minimize the number of testing pads. These measures give as a practical pad-placement method, that has little influcnce on LSI design. It was shown that the proposed method yieded a dramatic improvement of observability from 13-33% to 88-99% in actual layouts of 0.25-μm ASICs with 20k, and 390k gates. It was also found that local field effects from nearby wires are negligible for almost all the testing pads. This approach will enable the use of E-beam testing on LSIs made with 0.25-μm technology and the even more sophisticated process technologies to come.
社団法人電子情報通信学会の論文
1999-02-25