An IF-Band MMIC Chip Set for High-Speed Wireless Communication Systems

概要

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This paper proposes a set of three IF-band MMICs for high-speed wireless communication systems. The first of the circuits in this chip set is an MMIC logarithmic limiting receiver amplifier. This amplifier utilizes the self-phase distortion compensation technique, combining a common-source FET and a common-drain FET, to reduce phase distortion. The limiting characteristics were gain of more than 65 dB, 2.2-dBm saturated output power and phase deviation of less than 5°. A logarithmic accuracy of 2 dB and RSSI change coefficient of more than 11 mV/dB were also achieved. Typical power consumption was less than O.58 W with the supply voltages of +3 V and -2 V. The second of the fabricated circuits is an MMIC transmitter amplifier with more than 24-dB gain at 140 MHz. And the third of the fabricated circuits is an MMIC 90° signal divider and combiner. This MMIC combines a set of amplifiers with a set of dividers having a constant phase difference of 90°. Thus the isolation between the transmission port and the reception port is obtained. Thc chip size is less than 1/100 that of a commercial 140-MHz-band 90° coupler. At the frequency of 140 MHz, the mean transmission loss is about 2.1 dB for the divider part and 3.O dB for the combiner part. Furthermore, in the frequcncy range of 130 MHz to 150 MHz, signal leakage from the transmission port to the reception port is suppressed by more than 24 dB.
社団法人電子情報通信学会の論文
1998-01-25