A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application

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概要

• 論文の詳細を見る

• A low voltage dual V_T self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-V_T MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.

• 社団法人電子情報通信学会の論文
• 1997-08-25

著者

• YOO Hoi-Jun

  Department of EE. Korea Advanced Institute of Science and Technology (KAIST)

• Yoo H‐j

  Korea Advanced Inst. Sci. And Technol. Seoul Kor

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• A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application

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