A High-Tc Superconductor Josephson Sampler (Special Issue on Basic Properties and Applications of Superconductive Electron Devices)
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概要
- 論文の詳細を見る
This is a review of our high-T_c superconductor (HTS) sampler development. The design and experimental demonstration of a Josephson sampler circuit based on YBa_2Cu_3O_x(YBCO)/PrBa_2Cu_3O_x/YBCO ramp-edge junctions is described. The sampler circuit contains five edge junctions with a stacked YBCO groundplane and is based on single-flux quantum (SFQ) operations. Computer simulation results show that the time resolution of the sampler circuit depends strongly on the IcRn product of the junction and can be reduced to a few picoseconds with realistic parameter values. The edge junctions were fabricated using an in-situ process in which a barrier and a counter-electrode layer are deposited immediately after the edge etching without breaking the vacuum. The in-situ process improved the critical current uniformity of the junctions to 1σ=20% in twelve 4-μm-width junctions. An YBCO groundplane was placed on the junctions in a multilayer structure we call the HUG (H__-TS circuit with an u__-pper-layer g__-roundplane) structure. The inductance of YBCO lines was reduced to 1 pH per square without junction-quality degradation in the HUG structure. SFQ current-pulse generation, SFQ storage, and SFQ readout in the circuit have been confirmed by function tests using 3-kHz pulse currents. The successful operation of the sampler circuit has been demonstrated by measuring a signal-current waveform at 50K.
- 社団法人電子情報通信学会の論文
- 1997-10-25
著者
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Hidaka M
Istec/srl Tsukuba‐shi Jpn
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Hidaka Mutsuo
Istec/srl
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Hidaka Mutsuo
Fundamental Research Laboratories Nec Corporation
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Satoh Tetsuro
Fundamental Research Laboratories Resources And Environment Protection Research Laboratories Nec Cor
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Satoh Tetsuro
Istec/srl
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Satoh Tetsuro
Fundamental Research Laboratories Nec Corporation
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Tahara S
System Devices Research Laboratories Nec Corporation
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TAHARA Shuichi
Fundamental Research Laboratories, NEC Corporation
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TERAI Hirotaka
The author is with National Institute of Information and Communications Technology
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TERAI Hirotaka
Fundamental Research Laboratories, NEC Corporation
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