Partial Product Generator with Embedded Booth-Encoding

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概要

• 論文の詳細を見る

• In arithmetic units multiplication is a very important operation. It is a common approach to use the modified Booth's algorithm to reduce the number of partial products in a multiplication and speed it up. In this letter we show two circuits that fuse the usually separate functions of generating the partial products and selecting them. The circuits designed in DPL (Double Pass-transistor Logic) are bigger in MOS transistors, but are faster and, function at higher frequencies than a typical CMOS implementation. One of our circuits also has lower power consumption.

• 社団法人電子情報通信学会の論文
• 1995-12-25

著者

• Kaneko Kenji

  Corporate Research & Development Center Toshiba Corporation

• Pawlovsky Alberto

  Faculty of Engineering, Toin University of Yokohama

• Hanawa Makoto

  Central Research Laboratory (CRL), Hitachi Ltd.

• Kaneko Kenji

  Central Research Laboratory (CRL), Hitachi Ltd.

• Hanawa Makoto

  Central Research Laboratory (crl) Hitachi Ltd.

• Pawlovsky A

  Faculty Of Engineering Toin University Of Yokohama

• Kaneko Kenji

  Central Research Laboratory (crl) Hitachi Ltd.

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• Partial Product Generator with Embedded Booth-Encoding

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