A Distributed BIST Technique and Its Test Design Platform for VLSIs

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概要

• 論文の詳細を見る

• This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and a controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.

• 社団法人電子情報通信学会の論文
• 1995-11-25

著者

• Ogura Takeshi

  NTT LSI Laboratories

• Ikenaga Takeshi

  Ntt Lsi Laboratories

• Ogura Takeshi

  Ntt Lifestyle And Environmental Technology Laboratories

関連論文

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• On-Chip Multimedia Real-Time OS and Its MPEG-2 Applications
• A Distributed BIST Technique and Its Test Design Platform for VLSIs

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