Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC : SNUFEC VLSI (Special Issue on Multimedia, Analog and Processing LSIs)
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概要
- 論文の詳細を見る
An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-μm semi-custom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decoder VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.
- 社団法人電子情報通信学会の論文
- 1994-12-25
著者
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Kubota Shuji
NTT Radio Communication Systems Laboratories
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Kato Shuzo
NTT Radio Communication Systems Laboratories
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Kubota Shuji
Ntt R&d Management Dept.
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Kawazoe Katsuhiko
Ntt Radio Communication Systems Laboratories
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Honda Shunji
NTT Customer Systems Development Department
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