A PC-Based Scalable Parallel Resterizer Using Interleaved Scanline Rasterization

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概要

• 論文の詳細を見る

• We present a scalable parallel resterizer based on our interleaved scanline rasterization. The sorting overhead of a conventional scanline-based parallel rendering approach has been studied and removed by implementing a scanline assignment hardware. All advantages of the scanline-based parallel rendering are kept such that a good scalability and a small memory usage are achieved. Our architecture is evaluated precisely by a discrete event-based simulation, and the rendering performance and utilization are shown for a various number of rasterizers. The simulation results show more than 8 Mtriangles/s of performance with 64 rasterization engines running at 10 MHz.

• 社団法人電子情報通信学会の論文
• 2001-09-01

著者

• Kim J

  With The Department Of Electrical Engineering And Computer Science Korea Advanced Institute Of Scien

• Park K

  Korea Advanced Inst. Sci. And Technol. Taejon Kor

• Park Kyu

  With The Computer Engineering Research Laboratory Department Of Electrical Engineering And Computer

• Park Kyu

  With The Department Of Electrical Engineering And Computer Science Korea Advanced Institute Of Scien

• Kim Jun

  With The Computer Engineering Research Laboratory Department Of Electrical Engineering And Computer

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