A Fast and Efficient Output Scheduler for High-Performance Input Queueing ATM Switches

概要

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Many`output-scheduling' algorithms have been proposed for improving the performance of input queueing asynchronous transfer mode (ATM) switches, whereby cells from different random-access input queues destined for the same output can be scheduled for non-conflicting transmissions. An optimal output-scheduling algorithm, one with the full coordination of transmissions to all outputs, can approach the performance of output queueing. Because of the complexity of such an optimal scheduler, output schedulers proposed in the literature are without such coordination. We propose a simple way to incorporate such a full coordination in output-scheduling with much simple hardware, for small size switches. Throughput of the input queueing switch thus approaches that of the output queueing swicth, without speed-up, input/output grouping or complicated hardware. To make the output-scheduling algorithm fast enough, we incorporate parallelism and pipelining. We perform detailed simulation study of the performance of the input queueing switch with the proposed scheduling algorithm.
社団法人電子情報通信学会の論文
1998-03-25