Completion-Detection Techniques for Asynchronous Circuits (Special Issue on Asynchronous Circuit and System Design)

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概要

• 論文の詳細を見る

• An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and simulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.

• 社団法人電子情報通信学会の論文
• 1997-03-25

著者

• Kale Izzet

  School Of Electronic And Manufacturing Systems Engineering At The University Of Westminster

• GRASS Eckhard

  School of Electronic and Manufacturing Systems Engineering at the University of Westminster

• BARTLETT Viv

  School of Electronic and Manufacturing Systems Engineering at the University of Westminster

関連論文

• Completion-Detection Techniques for Asynchronous Circuits (Special Issue on Asynchronous Circuit and System Design)

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