Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design)

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概要

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• Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it (1) generates another PN or STG which is simpler than the original description and (2) produces an optimized net-list of an asynchronous controller in the target gate library while preserving the specified input-output behavior. An ability of back-annotating to the specification level helps the designer to control the design process. For transforming a specification petrify performs a token flow analysis of the initial PN and produces a transition system (TS). In the initial TS, all transitions with the same label are considered as one event. The TS is then transformed and transitions relabeled to fulfill the conditions required to obtain a safe irredundant PN. For synthesis of an asynchronous circuit petrify performs state assignment by solving the Complete State Coding problem. State assignment is coupled with logic minimization and speed-independent technology mapping to a target library. The final net-list is guaranteed to be speed-independent, i.e., hazard-free under any distribution of gate delays and multiple input changes satisfying the initial specification. The tool has been used for synthesis of PNs and PNs composition, synthesis and re-synthesis of asynchronous controllers and can be also applied in areas related with the analysis of concurrent programs. This paper provides an overview of petrify and the theory behind its main functions.

• 社団法人電子情報通信学会の論文
• 1997-03-25

著者

• Yakovlev Alexandre

  University Of Newcastle Upon Type

• KONDRATYEV Alex

  Cadence Berkeley Laboratories

• CORTADELLA Jordi

  Universitat Politecnica de Catalunya

• LAVAGNO Luciano

  Politecnico di Torino

• KISHINEVSKY Michael

  The University of Aizu

• KONDRATYEV Alex

  The University of Aizu

• Kishinevsky M

  The University Of Aizu

関連論文

• Design of Asynchronous Controllers with Delay Insensitive Interface(Special Section on VLSI Design and CAD Algorithms)
• Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design)
• Verification of asynchronous systems based on Petri Net unfoldings
• Synthesis of General Petri Nets
• Fast Instruction Cache Simulation for Hardware/Software Co-Design (Special Section on VLSI Design and CAD Algorithms)

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