ASYL-SdF: A Synthesis Tool for Dependability in Controllers (Special Issue on Synthesis and Verification of Hardware Design)

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概要

• 論文の詳細を見る

• Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.

• 社団法人電子情報通信学会の論文
• 1996-10-25

著者

• Saucier Gabriele

  Institut National Polytechnique de Grenoble

• Saucier G

  Institut National Polytechnique De Grenoble

• ROCHET Raphael

  Institut National Polytechnique de Grenoble

• LEVEUGLE Regis

  CSI

• Leveugle Regis

  Institut National Polytechnique De Grenoble/csi

関連論文

• FOREWORD (Special Issue on Synthesis and Verification of Hardware Design)
• ASYL-SdF: A Synthesis Tool for Dependability in Controllers (Special Issue on Synthesis and Verification of Hardware Design)
• Analysis of the Trends in Logic Synthesis (Special Issue on Synthesis and Verification of Hardware Design)

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