Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path

スポンサーリンク

概要

• 論文の詳細を見る

• For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose power-of-two DC gain is proposed. Output signal level can easily be compensated to that of input so that cascading many stages do not cause any gain errors, which are harmful in, for example, high precision measurement systems. The design is formulated as an optimization problem with magnitude response constraints. The integer linear programming modified for CSD codes is solved by the branch and bound method. The design example shows the effectiveness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field programmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the die area.

• 社団法人電子情報通信学会の論文
• 2001-08-01

著者

• Yamada Mitsuru

  The Authors Are With The Graduate School Of Science And Engineering Tokyo Institute Of Technology

• NISHIHARA Akinori

  The author is with Center for Research and Development of Educational Technology (CRADLE), Tokyo Ins

• Nishihara Akinori

  The Authors Are With The Graduate School Of Science And Engineering Tokyo Institute Of Technology

• Nishihara Akinori

  The Author Is With Center For Research And Development Of Educational Technology (cradle) Tokyo Inst

関連論文

• Code Optimization Technique for Indirect Addressing DSPs with Consideration in Local Computational Order and Memory Allocation
• Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path

スポンサーリンク