An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware

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概要

• 論文の詳細を見る

• This paper proposes a method for implementing a metric computation accelerator for fractal image compression using reconfigurable hardware. The most time-consuming part in the encoding of this compression is computation of metrics among image blocks. In our method, each processing element (PE) configured for an image block accelerates these computations by pipeline processing. Furthermore, by configuring the PE for a specific image block, we can reduce the number of adders, which are the main computing elements, by a half even in the worst case.

• 社団法人電子情報通信学会の論文
• 2001-01-01

著者

• Nagoya Akira

  The Author Is With Ntt Network Innovation Laboratories

• Nagano Hidehisa

  The Author Is With Ntt Communication Science Laboratories

• Matsuura Akihiro

  The Author Is With The Graduate School Of Informatics Kyoto University

関連論文

• An Efficient Implementation Method of a Metric Computation Accelerator for Fractal Image Compression Using Reconfigurable Hardware

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