Pattern-Based Maximal Power Estimation for VLSI Chip Design
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概要
- 論文の詳細を見る
In recently year, the analysis of power management becomes more important. It is difficult to obtain the maximum power because this is NP-complete. For an n-input circuit, there are 2^<2n> different input patterns to be considered. There are two major methods for this problem. First method is to generate input patterns to obtain the maximal power by simulating these generated patterns. This method is called pattern based. The other one uses probability method to estimate the power density of each node of a circuit to calculate the maximal power. In this paper, we use a pattern based method to estimate the maximal power. This method is better than that of probability for the simulation of power activity. In practical applications, these generated patterns can be applied and observe the activity of a circuit. These simulated data can be used to examined the critical paths for performance optimization. A simulated annealing algorithm is proposed to search input patterns for maximum power. Firstly, it transforms this problem into an optimization problem to adapt the simulated annealing method. In this method, there are three strategies for generating the next input patterns, called neighborhood. In the first strategy, it generates the next input pattern by changing the status of all input nodes. In the second strategy, some input nodes are selected and changed randomly. In the last strategy, it separates the input nodes into many groups and then selects one, randomly, to change its status. These different strategies have different solution space for the same input space. They will improve the searching speed and the accurate result. When a new result is accepted we use a Walk-Through method to search the local optimal result. To analyze the cost function in simulated annealing, a power dissipation model is proposed including the glitch phenomena, fanout load, and circuit type. For the criterion of equilibrium condition of annealing temperature, we use a statistical model to estimate the optimal iteration number in a temperature.
- 社団法人電子情報通信学会の論文
- 1997-11-25
著者
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Chen W‐j
National Taiwan Univ. Taipei Twn
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Feng Wu‐shiung
Department Of Electronic Engineering Chang Gung University
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Feng W‐s
Chang Gung Univ. Twn
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FENG Wu-Shiung
the Department of Electronic Engineering, Chang Gung University
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Feng Wu-shiung
The Department Of Electrical Engineering National Taiwan University
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CHEN Wang-Jin
the Department of Electrical Engineering, National Taiwan University
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Chen Wang-jin
The Department Of Electrical Engineering National Taiwan University
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