Optimal Loop Bandwidth Design for Low Noise PLL Applications (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications. Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.

• 1997-10-25

著者

• Choi Seung

  The Techno-economics Department At Etri

• Lim Kyoohyun

  The Electrical Engineering Department At Kaist

• KIM Beomsup

  the Electrical Engineering Department at KAIST

• Kim B

  Korea Advanced Inst. Of Sci. And Technol. (kaist) Daejeon Kor

関連論文

• Dual-Loop Digital PLL Design for Adaptive Clock Recovery (Special Section on VLSI Design and CAD Algorithms)
• Optimal Loop Bandwidth Design for Low Noise PLL Applications (Special Section on VLSI Design and CAD Algorithms)

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