A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs (Special Section on VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system requires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80 MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast, we consider the circuit structure of the FPGA along with the performance of its dedicated CAD system. We evaluate several FPGA logic-element structures with a technology mapping method. From these experiments, a multiplexor-based logic-element is found to be suitable for implementing such a high-speed circuit using the BDD-based technology mapping method. In addition, we examine how to best utilize the characteristics of the selected logic-cell structure in designing the wiring structure. It is found that the multiplexor-based cell can be connected efficiently in a clustered wiring structure.

• 社団法人電子情報通信学会の論文
• 1997-10-25

著者

• FUKAMI Kennosuke

  NTT Science and Core Technology Laboratory Group

• TAKAHARA Atsushi

  NTT System Electronics Laboratories

• HAYASHI Tsunemasa

  NTT System Electronics Laboratories

関連論文

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• Delay Calculation Method for SRAM-based FPGAs (Special Section on VLSI Design and CAD Algorithms)
• Low Power Management Method for PDS ONU Logic LSls
• A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs (Special Section on VLSI Design and CAD Algorithms)

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