LP Based Cell Selection with Constraints of Timing, Area, and Power Consumption

スポンサーリンク

概要

• 論文の詳細を見る

• This paper presents a new LP based optimal cell selection method. Optimal cell selection is useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle cycle time optimization. We also make a useful initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results, it can speed up a 13k-transistor circuit of a manual chip design by 17% without any increase of area.

• 一般社団法人電子情報通信学会の論文
• 1995-03-25

著者

• Tamiya Y

  Fujitsu Lab. Ltd. Kawasaki‐shi Jpn

• Tamiya Yutaka

  FUJITSU LABORATORIES LTD.

関連論文

• LP Based Cell Selection with Constraints of Timing, Area, and Power Consumption
• Path Mapping : Delay Estimation for Technology Independent Synthesis (Special Section on VLSI Design and CAD Algorithms)
• Robust Performance Optimization Using Padding Nodes and Separator Sets(Special Section on VLSI Design and CAD Algorithms)

スポンサーリンク