1/f Noise in Large Grain Poly-Si TFT's (Devices:先端デバイスの基礎と応用に関するアジアワークショップ)
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概要
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Existing models for low frequency excess electrical noise is scrutinized and a new model is proposed, in particular, for large grain poly-crystalline thin-film transistors. Major noise sources are supposed to be located in the grain boundary region and the grain boundary is modeled as two independent Schottky diode connected face-to-face. The experimentally observed behavior of the drain current noise spectral density, with respect to the current intensity and the barrier height, is successfully explained by our model. It is found that the noise sources are located near the grain boundary, spatially, and near the conduction band edge, energetically. The results are in good agreement with other reports on the location of defect states extracted from the low-frequency capacitance-voltage characteristics and current-voltage characteristics.
- 社団法人電子情報通信学会の論文
- 2003-06-24
著者
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Choi Won-jun
Nano Device Research Center Korea Institute Of Science And Technology
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Park Young
Nano Device Research Center Korea Institute Of Science And Technology
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HAN Il
Nano Device Research Center, Korea Institute of Science and Technology
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Lee Jungil
Nano Device Research Center, Korea Institute of Science and Technology
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Han Il
Nano Device Research Center Korea Institute Of Science And Technology
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Han Il
Nano Device Research Center Kist
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Lee Jungil
Nano Device Research Center Kist
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Park Young
Nano Device Research Center, Korea Institute of Science and Technology
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