Decoders for Double-Length SbEC-DbED Codes

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概要

• 論文の詳細を見る

• With the advent of high-density semiconductor chips, b-bit organized RAM chips have been fabricated and are now being marketed. Such memory systems use single b-bit byte error correcting and double b-bit byte error detecting codes (SbEC-DbED codes) to increase the reliability. This paper describes some new decoders for SbEC-DbED Reed-Solomon codes, with a data length of k = 128 bits and a byte length of b = 4 bits. Since these codes are based on Reed-Solomon codes, the decoders are constructed by using the regulality of the parity-matrix of Reed-Solomon codes and they have about 18 percent less gate circurity than conventional decoders.

• 一般社団法人情報処理学会の論文
• 1995-11-15

著者

• Kawano Tadasu

  Faculty Of Computer Science Hiroshima-denki Institute Of Technology

• Okano Hirokazu

  Faculty of Computer Science, Hiroshima-Denki Institute of Technology

関連論文

• Decoders for Double-Length SbEC-DbED Codes

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