Processor Accelerator Customization through Data Flow Graph Exploration

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概要

• 論文の詳細を見る

• To reduce the huge search space when customizing accelerators for the application specific instruction-set processor (ASIP), this paper proposes an automated customization method based on the data flow graph exploration. This method integrates the instruction identification and selection using an iterative improvement strategy, which uses a seed-growth algorithm to select the valid patterns that can bring higher performance enhancement. The search space is reduced by considering the performance factors during the identification stage. The experimental results indicate that the proposed method is feasible enough compared to the previous exhaustive algorithms.

• （社）電子情報通信学会の論文
• 2011-07-01

著者

• Bian Jinian

  Eda Lab Department Of Computer Science And Technology Tsinghua University

• Zhao Kang

  Eda Lab Department Of Computer Science And Technology Tsinghua University

• Zhao Kang

  Eda Lab Dep. Of Computer Sci. And Technol. Tsinghua Univ.

• Bian Jinian

  Eda Lab Dep. Of Computer Sci. And Technol. Tsinghua Univ.

関連論文

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• Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System
• Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design
• Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory
• Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation
• Processor Accelerator Customization through Data Flow Graph Exploration

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